1. Field of the Invention
This invention relates to magnetic memory cells and, more particularly, to magnetic memory cell junction compositions and shapes. In addition, the invention relates to a method for programming a memory cell including such junctions.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Recently, advancements in the use of magnetoresistive materials have progressed the development of magnetic random access memory (MRAM) devices to function as viable non-volatile memory circuits. In general, MRAM circuits exploit the electromagnetic properties of magnetoresistive materials to set and maintain information stored within individual magnetic memory cell junctions of the circuit. In particular, MRAM circuits utilize magnetization direction to store information within a memory cell junction, and differential resistance measurements to read information from the memory cell junction. More specifically, information is stored within an MRAM cell junction as a bit, the state of which is indicated by the direction of magnetization within one magnetic layer of the memory cell relative to another magnetic layer of the memory cell. In addition, a differential resistance can be determined from differences in the magnetization directions between magnetic layers of the memory cell such that the state of the bit stored in the MRAM cell junction may be read. Such an adaptation of the MRAM cell junction may include a magnetic layer having a fixed magnetic direction. Consequently, the layer may be referred to as the “pinned magnetic layer.” In addition, the layer may serve as a reference for another magnetic layer within the cell junction. The other magnetic layer, however, may be adapted to change its magnetic direction relative to the underlying pinned layer such that logic states of a bit may be stored within the magnetic cell junction. Consequently, the other magnetic layer may be referred to as the “storage layer” or “free magnetic layer.”
In some cases, an MRAM cell junction may be configured to manipulate the magnetic direction of the free magnetic layer into a direction that is parallel or antiparallel to the magnetic direction of the pinned magnetic layer. Note that the term “antiparallel” is used herein to describe a magnetic direction that is oriented 180° from the reference magnetic direction of the pinned magnetic layer. In this manner, the magnetic directions of the storage and pinned layers may be aligned such that a greater differential in resistance measurements may be obtained between different logic states of a bit. For example, in some cases, a MRAM cell junction may be configured to have an elliptical shape with an elongated dimension and a relatively shortened dimension. In general, magnetic moments within layers may naturally align with the periphery of the cell junction when no external magnetic field is applied, causing the magnetic direction of the junction to be set by the shape of the layers. Consequently, a majority of magnetic moments and thus, the overall magnetic direction, of an elliptically shaped magnetic junction may be aligned along the elongated dimension of the junction. In such an embodiment, the ease or difficulty of switching the state of the magnetic cell junction may depend on the shape of the junction. As explained below, variations within cell junction sizes and shapes, however, may cause the amount of current needed to switch memory cells to vary, reducing the reliability of the device. In addition, a cell junction configuration including elongated and shortened dimensions may undesirably occupy valuable surface area within the memory cell, preventing overall dimensions of the memory cell from being reduced.
Typically, an MRAM device includes a plurality of conductive lines with which to generate magnetic fields. The conductive lines may be spaced perpendicular to each other within a plane such that overlap points exist between the lines. The magnetic cell junctions, as described above, may be interposed between the conductive lines at such overlap points. In some cases, the conductive lines may be referred to as “bit” and “digit” lines. In general, “bit” lines may refer to conductive lines arranged in contact with magnetic cell junctions that are used for both write and read operations of the magnetic junctions. “Digit” lines, on the other hand, may refer to conductive lines spaced adjacent to the magnetic cell junctions that are used primarily during write operations of the magnetic cell junctions. An individual magnetic junction can be programmed by applying current simultaneously along a bit line and a digit line corresponding to the particular magnetic junction. Such an individual magnetic junction may herein be referred to as a selected magnetic junction, or the magnetic junction intentionally targeted for a writing procedure.
During the writing procedure, however, the multitude of memory cell junctions arranged along the bit line and the digit line corresponding to the selected cell junction will also sense current. Such memory cell junctions are herein referred to as half-selected cell junctions, or disturbed cell junctions since the magnetic field induced about them is generated from either a bit line or a digit line rather than both a bit line and a digit line. Even though less current is applied to these disturbed cells, variations within the cell junctions may allow a false bit to be unintentionally written to one or more of the disturbed cells. The variations present within an array may include variations in the shapes and sizes of magnetic cell junctions, as well as the presence of defects. Such variations of the cell junctions may cause the amount of current needed to switch memory cells in the array to vary, causing the write selectivity of the array to be reduced. Write selectivity, as used herein, may refer to the relative difference (i.e., current margin) between the amount of current responsible for switching the magnetization of a disturbed cell and the amount of current needed to switch the magnetization of a selected cell.
Therefore, it would be advantageous to develop a memory cell that increases the write selectivity of a magnetic memory array. In particular, it would be advantageous to develop a memory cell which negates the issue of write selectivity with a memory array. For example, it may be advantageous to fabricate a magnetic cell junction with layers having magnetic directions that do not depend on the shape of the junction. In addition, it would be beneficial to develop a memory cell which decreases the surface area consumed by the cell such that a denser memory circuit may be effectively fabricated. Moreover, it would be additionally or alternatively beneficial to fabricate a magnetic cell junction which allows an increased differential resistance to be determined between magnetic layers of the cell junction. Such a junction may allow the logic state of the bit stored in the MRAM cell junction to be more accurately read.